AES: Advanced Encryption Standard Core
GENERAL DESCRIPTION
LancsNet AES fully supports NIST FIP-197 standards and is a bandwidth-resource scalable AES engine. Our implementation permits pipeline stages can be configured by end-users to achieve the desired bandwidth ranging from 2-16Gbps. The core is ready to be adopted for popular NIST cipher modes such as ECB, CBC, OFB, CFB, CTR. AES currently is adopted as the major encryption/decryption workhorse in many protocols and applications (AES-GCM, ESP, TLS).
KEY FEATURES
Features
-
-
-
-
- Scalable throughput up to 16 Gbps
- NIST FIP-197 compliant
- Processes 128-bit data blocks with 8, 16, or 32-bit data interface
- Employs key sizes of 128-bit 192-bit, or 256-bit
- Includes the key expansion function.
- Optional parity check feature for data integrity
-
-
-
Configurability
-
-
-
- Tunable pipeline stages and throughput
- Processes 128-bit data blocks with 8, 16, or 32-bit data interface
- LUT-based S-box or RAM-based S-box
-
-
Technology Agnostic
-
-
-
- VHDL source code available, designed and tested for FPGA* and ASIC
-
-
* In production with customers
Example Implementation – LancsNet AES (area-optimized version)
| Family | Part |
Fmax (MHz) |
LUT | LUTRAM | FF | BRAM | DSP | IP Config |
| Artix7 | XC7A100T | 292.74 | 1232 | 0 | 1041 | 0 | 0 | AES-128, 1 Round |
| Kintex7 | XC7K325T | 385.80 | 1232 | 0 | 1041 | 0 | 0 | AES-128, 1 Round |
| Virtex7 | XC7VX550T | 415.97 | 1232 | 0 | 1041 | 0 | 0 | AES-128, 1 Round |
| Artix7 | XC7A100T | 260.15 | 1329 | 0 | 1265 | 0 | 0 | AES-192, 1 Round |
| Kintex7 | XC7K325T | 342.70 | 1329 | 0 | 1265 | 0 | 0 | AES-192, 1 Round |
| Virtex7 | XC7VX550T | 368.32 | 1329 | 0 | 1265 | 0 | 0 | AES-192, 1 Round |
| Artix7 | XC7A100T | 261.64 | 1413 | 0 | 1425 | 0 | 0 | AES-256, 1 Round |
| Kintex7 | XC7K325T | 342.58 | 1413 | 0 | 1425 | 0 | 0 | AES-256, 1 Round |
| Virtex7 | XC7VX550T | 367.78 | 1413 | 0 | 1425 | 0 | 0 | AES-256, 1 Round |
Example Implementation – LancsNet AES (performance-optimized version)
| Family | Part |
Fmax (MHz) |
LUT | LUTRAM | FF | BRAM | DSP | IP Config |
| Artix7 | XC7A100T | 296.38 | 7392 | 1 | 3468 | 0 | 0 | AES-128, 14 Round |
| Kintex7 | XC7K325T | 383.87 | 7392 | 1 | 3468 | 0 | 0 | AES-128, 14 Round |
| Virtex7 | XC7VX550T | 415.80 | 7392 | 1 | 3468 | 0 | 0 | AES-128, 14 Round |
| Artix7 | XC7A100T | 262.81 | 8918 | 1 | 4204 | 0 | 0 | AES-192, 14 Round |
| Kintex7 | XC7K325T | 346.86 | 8918 | 1 | 4204 | 0 | 0 | AES-192, 14 Round |
| Virtex7 | XC7VX550T | 372.57 | 8918 | 1 | 4204 | 0 | 0 | AES-192, 14 Round |
| Artix7 | XC7A100T | 259.94 | 10259 | 1 | 4876 | 0 | 0 | AES-256, 14 Round |
| Kintex7 | XC7K325T | 339.67 | 10244 | 1 | 4876 | 0 | 0 | AES-256, 14 Round |
| Virtex7 | XC7VX550T | 364.43 | 10244 | 1 | 4876 | 0 | 0 | AES-256, 14 Round |
APPLICATIONS
IPsec hardware accelerators, security gateway, data center acceleration, edge router, edge networking for IoT data aggregation, specialized authenticated encrypt/decrypt devices.
An example application of the core in AES-GCM engine
DELIVERABLES
The IP core and the simulation testbench are provided with extensive documentation and technical support from our technical teams. By default, the encrypted format IP core is provided, full source code is available for interested partners/developers under a specific agreement
FOR DEMO ON HARDWARE AND SIMULATION
Contact us sales@lancsnet.com
PRICING AND FURTHER INFORMATION
Request for quote & datasheet at sales@lancsnet.com
Recent Comments