L2SW-T: Fully customizable L2 switch core for high throughput and low latency applications
LancsNet L2 FPGA-based switching core for high throughput and low latency (L2SW-T). FPGA The core design adopts most of our innovative IPs for delivering the best and reliable network performance for critical applications such as cell-site routers, rugged network switches. L2SW-T is a fully functional and Tbps-level bandwidth Ethernet switching plane. This is an integrated design for the L2 data plane adopting several Lancsnet innovative cores, including Lancsnet -PSM, Lansnet L2_ACL, Lansnet L2 MAC and is ready to be jointly developed with Lancsnet NOS and Lancsnet Embedded platform. The design is meticulously optimized for performance and packet latency, still practically proven to be a cost-effective solution. The core offers an open fundamental platform for deploying applications at the higher level such as network monitoring, network filtering, network traffic management, and a firewall.
- Support up to 64 physical interface
- 16K CAM-based MAC table
- 1K L2/L3-ACL entries
- Support up to 4K VLAN_IDs
- QoS configuration and monitoring
- Support rollback and remove faulty packets
- Supports IEEE 802.1Q, multicast, and broadcast
- Support 1G/10G/25G/100G interfaces
- Up to 200Gbps switching capability
- Packet latency 64-byte/1514-byte : 1.304 / 13.384
- Support jumbo packet for all channels
- AMBA 4 AXI4-Stream compatible
- Configurable bus size, buffer size.
- Adjustable network interfaces
- Support uniform and arbitrary packet sizes.
- Adaptable for any packet switching applications
- On-demand specs customization
- VHDL source code available, designed and tested for FPGA* and ASIC ready
* In production with customers
Example Implementation – LancsNet L2SW-T
Switching core for networking devices (L2, L3 switch, router, NGFW, home, and enterprise), network aggregator, network accelerators, network tapping.
An example application of the L2SW-T IP in Router design
The IP core and the simulation testbench are provided with extensive documentation and technical support from our technical teams. By default, the encrypted format IP core is provided, full source code is available for interested partners/developers under a specific agreement
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