LancsNet Neo

Firmware Development Kit (FDK) and IP Cores

A number of innovations shape tomorrow’s brilliantly organize stage. By advancing these advances we advance the arrange stage, a stage that will in a general sense alter the way our social orders improve, collaborate, deliver, administer and live reasonably. This will not as it were alter the telecom industry, it’ll make modern openings for other businesses and distinctive sorts of trade models. 

LANCS NET Research areas for future technologies

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Future network security

A next-generation firewall (NGFW) is a network security device that provides capabilities beyond a traditional, stateful firewall.

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Future IoT

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5G evolution and 6G

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LANCS NET – SHARED MEMORY IP

SH1

Shared memory IP: Sequential packet buffering architecture

LancsNet sequential shared memory (SSM) IP is an innovative and high-performance packet buffer IP that is well suited for medium and high-bandwidth (up to 100Gbps) applications. The logic control is meticulously optimized for the area while offering decent performance. The design is highly configurable and is provided a convenient AMBA 4 AXI4-Stream interface for easy system integration.

sh2

Shared memory IP: Parallel packet buffering architecture

LancsNet parallel shared memory (PSM) IP is an innovative and high-performance packet buffer IP that is well suited for high and ultra-high bandwidth (up to 200 Gbps) applications. The memory is design to buffer multiple Ethernet streams simultaneously and eliminates the need for local line card buffers as well as avoiding HOL blocking effect. The design is highly configurable and is provided a convenient AMBA 4 AXI4-Stream interface for easy system integration.

LANCS NET – LAYER II SWITCHING IP

Sw1

L2SW-EH: Fully customizable L2 switch core for Cost-effective Enterprise and Home applications

LancsNet L2 switching enterprise and home version (L2SW-EH) IP is one of the featured and core-valued designs offered by our FPGA team. L2SW-EH IP is a fully functional and high bandwidth (~100Gbps) L2 switching core. This is an integrated design for the L2 data plane adopting several Lancsnet innovative cores, including Lancsnet -SSM, LancsNet L2_ACL, LancsNet L2 MAC and is ready to be jointly developed with Lancsnet NOS and Lancsnet Embedded platform. 

sw2

L2SW-T: Fully customizable L2 switch core for high throughput and low latency applications

LancsNet L2 FPGA-based switching core for high throughput and low latency (L2SW-T).  FPGA The core design adopts most of our innovative IPs for delivering the best and reliable network performance for critical applications such as cell-site routers, rugged network switches. L2SW-T is a fully functional and Tbps-level bandwidth Ethernet switching plane.  This is an integrated design for the L2 data plane adopting several Lancsnet innovative cores, including Lancsnet -PSM, Lansnet L2_ACL, Lansnet L2 MAC and is ready to be jointly developed with Lancsnet NOS and Lancsnet Embedded platform. 

LANCS NET – LOOKUP IP

CAM1

UF-CAM: CAM-based Fast pattern matching engine

LancsNet UF-CAM is a specialized engine designed for ultra-fast lookup operations. Regardless of the look-up pattern length and nature, the engine could perform a lookup every clock cycle with deterministic latency. The dual-port interface allows the update operation is performed independently without degrading lookup operation. Proprietary techniques are applied that ensures virtually zero collision rate in the most practical applications. This engine is currently adopted in the Lancsnet mainstream products.

TCAM

TCAM: Scalable Ternary Content Address Memory

LancsNet TCAM IP is specialized optimized and design for lookup operation in most networking applications. The most state-of-the-art techniques have been adopted, e.g., multi-pumping-enabled allow to simulate multiport memory, which enhances memory utilization. The design is flexibly provided with all configurable parameters and is targeted for major intelligent network filter engines such as L2-,L3-ACL, stateful lookup.

LPM

LPM-CAM: Longest-prefix match based on CAM

LancsNet LPM-CAM performs the Longest Match Routing algorithm used by IP routers to select an entry from a routing table. The router uses the longest (prefix) match to determine the egress (outbound) interface and the address of the next device to which to send a packet. Our specialized LPM-CAM IP is cascaded by multiple CAM memory in parallel that allows storing and loop-up simultaneously many IP prefixes with decent bandwidth and minimum latency. The provided RTL core can be easily customized and optimized for the need of specific IP ranges and prefixed.

LANCS NET – SECURITY IP

aes

AES: Advanced Encryption Standard Core

LancsNet AES fully supports NIST FIP-197 standards and is a bandwidth-resource scalable AES engine. Our implementation permits pipeline stages can be configured by end-users to achieve the desired bandwidth ranging from 2-16Gbps. The core is ready to be adopted for popular NIST cipher modes such as ECB, CBC, OFB, CFB, CTR. AES currently is adopted as the major encryption/decryption workhorse in many protocols and applications (AES-GCM, ESP, TLS).

AES GCM

AES-GCM: Scalable Authenticated Encrypt/Decrypt Engine

LancsNet AES-GCM fully supports NIST SP 800-38D and FIP-197 standards. This is a scalable AES-GCM design that could be configured for desired bandwidth from 2-16Gbps by the trade-off in area. The core is encapsulated with friendy interfaces and is ready for employed in applications such as Secure Real-time Transport Protocol (SRTP – IETF RFC 7714) and Transport Layer Security (TLS – IETF RFC 5228).

IPSec

IPSec-ESP: Encapsulating Security Payload for IP Security Suite

LancsNet IPsec-ESP Engine is designed to provide hardware acceleration of the ESP packet processing required to implement in IPSec compliant devices. The design offers straightforward for offloading ESP packet processing to hardware up to 25.6 Gbps while high-level protocols such as connection establishment/management, SA, Key exchange are run on embedded CPU. The core follows strictly recommendations from IETF RFC 4303/RFC 4301 and has been extensively tested in association with our products.

LANCS NET – OTHER IP

MTG

MNTG: Multistream network traffic generator

LancsNet Multistream network traffic generator (MSNTG) is the highly customizable and configurable network traffic generator IP that supports all types of L2 and L3 traffics. The cores can be used for multistream generations for network devices such as routers and switch with a large number of physical interfaces. The core can generate random or user-defined packets and include the self-check module for automatic testing. A full solution offered by LancsNet includes the MNTG IP, the hardware chassis, and the software running on PC for config the test cases.

RO FUB

RO-PUF: Physically Unclonable Functions for critical security applications

LancsNet RO-PUF is a patented design of Ring Oscillator Physically-unclonable Functions (PUFs) which allow extracting the unique device pattern. This is targeted for critical security applications including but not limited to: hardware authentication (ID authentication), unpredictable PRNG, unique unclonable key generator.