LPM-CAM: Longest-prefix match based on CAM

GENERAL DESCRIPTION

LancsNet LPM-CAM performs the Longest Match Routing algorithm used by IP routers to select an entry from a routing table. The router uses the longest (prefix) match to determine the egress (outbound) interface and the address of the next device to which to send a packet. Our specialized LPM-CAM IP is cascaded by multiple CAM memory in parallel that allows storing and loop-up simultaneously many IP prefixes with decent bandwidth and minimum latency. The provided RTL core can be easily customized and optimized for the need of specific IP ranges and prefixed.

LPM
KEY FEATURES

Features

          • Support all prefix length (/0 to /32)
          • Fully pipelined design for lookup operation every clock cycle
          • Fixed 5-cycle latency for lookup operation (15-20ns) when internal memory is used
          • Maximum  >300M lookup/s **
          • Optionally utilizing external memory for large entries (lower latency)

**20K/28K entries, 4-sub CAMs on Xilinx Kintex7 and Virtex 7

Configurability

        • Memory-mapped AXI4-lite
        • Total entries
        • Hash functions
        • Number of prefix tables for parallel lookup
        • (optional) switchable between internal and external memory.

Technology Agnostic

        • VHDL source code available, designed and tested for FPGA* and ASIC

* In production with customers

Example Implementation – LancsNet LPM-CAM (area-optimized version)

Family Part

Fmax

(MHz)

LUT LUTRAM FF BRAM DSP IP Config

Artix7

XC7A200T

244.6

564

0

483

29

0

20K entries

Kintex7

XC7K325T

317.6

564

0

483

29

0

20K entries

Virtex7

XC7VX550T

323.6

564

0

483

29

0

20K entries

Artix7

XC7A200T

244.6

684

0

565

40

0

28K entries

Kintex7

XC7K325T

317.6

684

0

565

40

0

28K entries

Virtex7

XC7VX550T

323.6

684

0

565

40

0

28K entries

    APPLICATIONS

    L3 Switch and Router, NG Firewall, Network aggregator, network accelerators

     An example application of the LPM-CAM in Router FIB lookup, L3 switch core

    lpm app
    DELIVERABLES

    The IP core and the simulation testbench are provided with extensive documentation and technical support from our technical teams. By default, the encrypted format IP core is provided, full source code is available for interested partners/developers under a specific agreement

    FOR DEMO ON HARDWARE AND SIMULATION
    PRICING AND FURTHER INFORMATION

    Request for quote & datasheet at sales@lancsnet.com