LancsNet Neo

Firmware Development Kit (FDK) and IP Cores

All core are designed by LancsNet and fully licensed by LANCS.,JSC optional RTL source code include, fully FPGA proven and/or ASIC ready, except PUF core

Layer II Switching IP Core


 L2SW-EH: Fully customizable L2 switch core for Cost-effective Enterprise and Home applications

LancsNet L2 switching enterprise and home version (L2SW-EH) IP is one of the featured and core-valued designs offered by LancsNet. L2SW-EH IP is a fully functional and high bandwidth (100Gbps) L2 switching core.


L2SW-T: Fully customizable L2 switch core for high throughput and low latency applications

LancsNet L2 FPGA-based switching core for high throughput and low latency (L2SW-T).  The FPGA core design adopts most of our innovative IPs for delivering the best and reliable network performance for critical applications such as cell-site routers, rugged network switches. 

Shared Memory IP Core


Shared memory IP: Sequential packet buffering architecture

LancsNet sequential shared memory (SSM) IP is an innovative and high-performance packet buffer IP that is well suited for medium and high-bandwidth (up to 100Gbps) applications.


Shared memory IP: Parallel packet buffering architecture

LancsNet parallel shared memory (PSM) IP is an innovative and high-performance packet buffer IP that is well suited for high and ultra-high bandwidth (up to 200 Gbps) applications. 

Lookup IP Core


UF-CAM: CAM-based Fast pattern matching engine

LancsNet UF-CAM is a specialized engine designed for ultra-fast lookup operations. Regardless of the look-up pattern length and nature, the engine could perform a lookup every clock cycle with deterministic latency.


TCAM: Scalable Ternary Content Address Memory

LancsNet TCAM IP is specialized optimized and design for lookup operation in most networking applications. The most state-of-the-art techniques have been adopted, e.g., multi-pumping-enabled allow to simulate multiport memory, which enhances memory utilization. 


LPM-CAM: Longest-prefix match based on CAM

LancsNet LPM-CAM performs the Longest Match Routing algorithm used by IP routers to select an entry from a routing table. The router uses the longest (prefix) match to determine the egress (outbound) interface and the address of the next device to which to send a packet. 

Security IP Core


AES: Advanced Encryption Standard Core

LancsNet AES fully supports NIST FIP-197 standards and is a bandwidth-resource scalable AES engine. Our implementation permits pipeline stages can be configured by end-users to achieve the desired bandwidth ranging from 2-16Gbps. 


AES-GCM: Scalable Authenticated Encrypt/Decrypt Engine

LancsNet AES-GCM fully supports NIST SP 800-38D and FIP-197 standards. This is a scalable AES-GCM design that could be configured for desired bandwidth from 2-16Gbps by the trade-off in area. 


IPSec-ESP: Encapsulating Security Payload for IP Security Suite

LancsNet IPsec-ESP Engine is designed to provide hardware acceleration of the ESP packet processing required to implement in IPSec compliant devices. 

Other IP Core


MNTG: Multistream network traffic generator

LancsNet Multistream network traffic generator (MSNTG) is the highly customizable and configurable network traffic generator IP that supports all types of L2 and L3 traffics. 


RO-PUF: Physically Unclonable Functions for critical security applications

LancsNet RO-PUF is a patented design of Ring Oscillator Physically-unclonable Functions (PUFs) which allow extracting the unique device pattern.