TCAM: Scalable Ternary Content Address Memory

GENERAL DESCRIPTION

LancsNet TCAM IP is specialized optimized and design for lookup operation in most networking applications. The most state-of-the-art techniques have been adopted, e.g., multi-pumping-enabled allow to simulate multiport memory, which enhances memory utilization. The design is flexibly provided with all configurable parameters and is targeted for major intelligent network filter engines such as L2-,L3-ACL, stateful lookup.

TCAM
KEY FEATURES

Features

          • Fully pipelined, allow look up every clock cycle
          • Fixed lookup latency 7 clock cycles
          • Independent lookup and updating
          • Device-specific optimization
          • Multi-Pumping architecture for area optimization
          • Achieve matching/filtering performance of 300-400M lookup per second**

** tested with Series 7 Xilinx FPGA device

Configurability

        • Configurable pipeline stages
        • Configurable TCAM Depth and Width.
        • Configurable multi-pumping factor
        • Configurable sub-memory block to LUT or BRAM for maximum resource efficiency

Technology Agnostic

        • VHDL source code available, designed and tested for FPGA* and ASIC

* In production with customers

Example Implementation – LancsNet SSM

Family Part

Fmax

(MHz)

LUT LUTRAM FF BRAM DSP IP Config
Artix7 XC7A200T 342 9K 0 16K 112 0 1008 x 128-bit BRAM based
Kintex7 XC7K325T 376 9K 0 16K 112 0 1008 x 128-bit BRAM based
Virtex7 XC7VX550T 392 9K 0 16K 112 0 1008 x 128-bit BRAM based
Artix7 XC7A200T 346 33K 20K 24K 0 0 1008 x 128-bit BRAM based
Kintex7 XC7K325T 447 33K 20K 24K 0 0 1008 x 128-bit BRAM based
Virtex7 XC7VX550T 466 33K 20K 24K 0 0 1008 x 128-bit BRAM based

    APPLICATIONS

    Computing engine in major network devices (L2, L3 Switch, Router, NGFW), data compression, network security application, Intrusion prevention system, Hardware accelerator for pattern searching/matching, artificial neural network, hardware-based deep packet inspection.

     An example application of the core in Router/Switch MAC lookup

    TCAM app
    DELIVERABLES

    The IP core and the simulation testbench are provided with extensive documentation and technical support from our technical teams. By default, the encrypted format IP core is provided, full source code is available for interested partners/developers under a specific agreement

    FOR DEMO ON HARDWARE AND SIMULATION
    PRICING AND FURTHER INFORMATION

    Request for quote & datasheet at sales@lancsnet.com