Shared memory IP: Sequential packet buffering architecture

GENERAL DESCRIPTION

LancsNet sequential shared memory (SSM) IP is an innovative and high-performance packet buffer IP that is well suited for medium and high-bandwidth (up to 100Gbps) applications. The logic control is meticulously optimized for the area while offering decent performance. The design is highly configurable and is provided a convenient AMBA 4 AXI4-Stream interface for easy system integration.

SH1
KEY FEATURES

Features

        • Up to ~100 Gbps throughput
        • Support max 64 channel IDs
        • Raw packet latency: 16 ns/192 ns 64-byte/1514-byte packets (for single interface)
        • Memory-efficiency: 50%-100% depended on the packet size.
        • Supports variable packet length from 64 – 9600 bytes
        • AXI-stream4 compatible
        • Fault-tolerant and soft-error auto-recovery (optional with extra logic overhead)
        • Status monitoring (optional with extra logic overhead

Configurability

        • Core bus size from 128-4,096 bit
        • Memory size: depending on the availability.
        • Extra reliability features

Technology Agnostic

        • RTL source code available, designed and tested for FPGA* and ASIC

* In production with customers

Example Implementation – LancsNet SSM

    Sh1 table
    APPLICATIONS

    L2, L3 switch and routers, NGFW, network aggregator, network accelerators, network tapping

     An example application of the SSM IP in L2 switch

    Sh1 app
    DELIVERABLES

    The IP core and the simulation testbench are provided with extensive documentation and technical support from our technical teams. By default, the encrypted format IP core is provided, full source code is available for interested partners/developers under a specific agreement

    FOR DEMO ON HARDWARE AND SIMULATION
    PRICING AND FURTHER INFORMATION

    Request for quote & datasheet at sales@lancsnet.com